A configuration is disclosed for directly sampling high frequency signals on a discrete-time basis and performing a reception process on the result, in order to achieve reductions in size and power consumption of a radio receiver and integration of an analog signal processing section and a digital signal processing section (e.g., see Patent Literature 1).
An example configuration and operation of a discrete-time direct sampling circuit using a conventional discrete-time process will be described with reference to FIG. 1. FIG. 1 shows the discrete-time direct sampling circuit as a whole. The discrete-time direct sampling circuit includes voltage current converter (TA) 1, sampling switch 2, history capacitor (CH) 3, rotation capacitors 4a to 4h, buffer capacitor (CB) 5, dump switch 6, reset switch 7, integral switches 8a to 8h, release switches 9a to 9h, and digital control unit 10.
Voltage current converter (TA) 1 converts received radio frequency (RF) signals into current, and outputs the current as analog RF current signals. Sampling switch 2 is composed of, for example, PET, and samples received analog RF current signals depending on input of local frequency signal (LO).
History capacitor (CH) 3 accumulates electric charge supplied by the current output from sampling switch 2. Rotation capacitors 4a to 4h are each connected in parallel to both history capacitor 3 and buffer capacitor 5 via several switches. In addition, each of rotation capacitors 4a to 4h consists of rotation capacitor (CR) for accumulating or discharging the electric charge in response to “on” or “off” controls of the switches.
Buffer capacitor (CB) 5 is commonly connected to a plurality of rotation capacitors 4 to buffer charge signals by sharing the electric charge accumulated in capacitors 4. Dump switch 6 turns on or off connections between respective rotation capacitors 4a to 4h and buffer capacitor 5. After the electric charge shared with buffer capacitor 5, reset switch 7 grounds the electric charge accumulated in rotation capacitor 4.
A group of integral switches 8a to 8h consists of a plurality of integral switches. In addition, integral switches 8a to 8h turn on or off connections between history capacitor 3 and respective rotation capacitors 4a to 4h. A group of release switches 9a to 9h consists of a plurality of release switches. In addition, release switches 9a to 9h turn on or off connections between respective rotation capacitors 4a to 4h and buffer capacitor 5.
Dump switch 6, reset switch 7, integral switches 8a to 8h, and release switches 9a to 9h are composed of (n type) FETs, for example. The n-type FET is turned on (electrically conducted) at high gate voltage (hereinafter, referred to as “high state”), and is turned off (disconnected) at a low gate voltage. (hereinafter, referred to as “low state”).
Digital control unit 10 generates control signals and supplies the control signals to integral switches 8a to 8h, release switches 9a to 9h, dump switch 6, and reset switch 7.
In this case, eight rotation capacitors CR are provided in the discrete-time direct sampling circuit as an example. Eight integral switches 8a to 8h and eight release switches 9a to 9h are also provided. After each component number, “a” to “h” are attached in alphabetical order. In fact, the discrete-time direct sampling circuit can have a configuration for performing differential operation, and such a configuration is disclosed in Patent Literature 1. However, for simplification of explanation, the description will be omitted.
FIG. 2 is a timing diagram of the control signals generated by digital control unit 10. Local frequency signal (LO) is supplied to the gate of sampling switch 2. Control signals S1 to S8 are supplied to the gates of integral switches 8a to 8h, respectively. Control signal SAZ is supplied to the gates of release switches 9a to 9d. Control signal SBZ is supplied to the gates of release switches 9e to 9h. Control signal D is supplied to the gate of dump switch 6, and control signal R is supplied to the gate of reset switch 7.
An operation of the discrete-time direct sampling circuit shown in FIG. 1 will now be described. Voltage current converter 1 converts received analog RF signals into analog RF current signals and outputs the result to sampling switch 2. Sampling switch 2 samples the analog RF current signals based on local frequency signal LO having the almost same frequency as the analog RF current signals. The signals sampled based on local frequency signal LO is turned into discrete signals, which is timely discrete, through charge integration in history capacitor 3 and rotation capacitors 4a to 4h. 
History capacitor 3 and one of rotation capacitors 4a to 4h define parallel-connected capacitors. Such capacitors can integrate the discrete signals over a longer time than the clock length of local frequency signal LO. Consequently, a filtering process and decimation are performed.
To be more specific, the discrete-time direct sampling circuit first turns on integral switch 8a by control signal S1, and then connects rotation capacitor 4a to history capacitor 3. The electric charge, which is supplied to the two types of capacitors during the high state of control signal S1 (for example, for eight periods of local frequency signal LO), is integrated.
During the low state of control signal S1, history capacitor 3 is disconnected from rotation capacitor 4a and then is connected to rotation capacitor 4b by control signal S2. Rotation capacitor 4b integrates the electric charge supplied by current of the discrete signals during the high state of control signal S2, and then is disconnected from history capacitor 3. In the same way, rotation capacitors 4c to 4h are connected in sequence to history capacitor 3 every eight periods of local frequency signal LO by control signals S3 to S8, respectively. Thus, the two types of capacitors integrate the electric charge supplied by the current of the discrete signals.
As described above, the discrete-time direct sampling circuit integrates electric charge, which is supplied by current of discrete signals for eight periods of local frequency signal LO. Consequently, the discrete-time direct sampling circuit can achieve filtering characteristics of a finite impulse response (FIR) filter composed of eight taps. In addition, integrating signals in the eight periods of local frequency signal LO can obtain the amount of electric charge for one sample, and thus the sampling rate is decimated into one-eighth. A function section to achieve this filtering characteristics is referred to as “first FIR filter.”
Additionally, the discrete-time direct sampling circuit connects rotation capacitors 4a to 4h in sequence to history capacitor 3 to achieve filtering characteristics of an infinite impulse response (IIR) filter. A function section to achieve this filtering characteristics is referred to as “first IIR filter.”
Next, control signal SAZ turns on release switches 9a to 9d to electrically conduct rotation capacitors 4a to 4d to buffer capacitor 5. Thus, the electric charge accumulated in rotation capacitors 4a to 4d is shared with buffer capacitor 5. As a result, the electric charge of rotation capacitors 4a to 4d partially moves to and accumulates into buffer capacitor 5.
After rotation capacitors 4a to 4d and buffer capacitor 5 share the electric charge, control signal D turns off dump switch 6 to dissolve the state of sharing the electric charge. Next, control signal R turns on reset switch 7, and then grounding resets the remaining electric charge in rotation capacitors 4a to 4d. 
By this means, the discrete-time direct sampling circuit can achieve the filtering characteristics of a FIR filter composed of four taps, by partially moving the electric charge accumulated in rotation capacitors 4a to 4d to buffer capacitor 5 to combine the moved electric charge. The discrete-time direct sampling circuit combines discrete signals for four samples into discrete output signals for one sample, and then the sampling rate is decimated into a quarter.
Similarly, control signal SBZ turns on release switches 9c to 9h, and rotation capacitors 4e to 4h partially share the electric charge accumulated therein with buffer capacitor 5. Accordingly, the discrete-time direct sampling circuit achieves filtering characteristics of the FIR filter composed of four taps and the quarter decimation. The circuit having such filtering characteristics is referred to as “second FIR filter.”
In addition, the discrete-time direct sampling circuit allows each group of rotation capacitors 4a to 4d and 4e to 4h to alternately share the electric charge with buffer capacitor 5, to achieve the IIR filtering characteristics. The circuit having such filtering characteristics is referred to as “second IIR filter.”
FIG. 3 shows the filtering characteristics described above. In this case, the frequency of local frequency signal LO is 2.4 GHz, the capacitance of history capacitor 3 is 15 pF, the capacitance of each of the rotation capacitors 4a to 4h is 0.5 pF, and the capacitance of buffer capacitor 5 is 15 pF. The transconductance of voltage current converter 1 is 7.5 mS.
FIG. 3A shows filtering characteristics of the first FIR filter, and FIG. 3 shows filtering characteristics of the first IIR filter. FIG. 3C shows filtering characteristics of the second FIR filter, and FIG. 3D shows filtering characteristics of the second IIR filter. FIG. 3E shows filtering characteristics of the whole discrete-time direct sampling circuit, and FIG. 3F shows an expanded view of the frequency range in the vicinity of 2.4 GHz in the filtering characteristics of FIG. 3E. In the FIGs, the DC gain is normalized with 0 dB.
As described above, the discrete-time direct sampling circuit combines filtering characteristics of the first FIR filter, the first IIR filter, the second FIR filter, and the second IIR filter, and outputs signals subjected to a filtering process of the combined characteristics, to a circuit in a subsequence stage.